puts "Start to source [info script]"
global SLR2_DPU_V3_TOP  
set_property LOC RAMB36_X0Y120  [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[0].ram_18_0_6_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y124  [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[1].ram_18_0_6_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y128  [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[2].ram_18_0_6_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y132 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[3].ram_18_0_6_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y136 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[4].ram_18_0_6_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y140 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[5].ram_18_0_6_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y144 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[6].ram_18_0_6_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y148 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[7].ram_18_7_13_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y152 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[8].ram_18_7_13_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y156 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[9].ram_18_7_13_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y160 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[10].ram_18_7_13_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y164 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[11].ram_18_7_13_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y168 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[12].ram_18_7_13_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y172 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[13].ram_18_7_13_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y176 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[14].ram_18_14_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
## ===========================================
set_property LOC RAMB36_X1Y120 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[15].ram_18_15_21_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y124 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[16].ram_18_15_21_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y128 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[17].ram_18_15_21_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y132 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[18].ram_18_15_21_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y136 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[19].ram_18_15_21_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y140 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[20].ram_18_15_21_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y144 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[21].ram_18_15_21_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y148 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[22].ram_18_22_28_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y152 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[23].ram_18_22_28_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y156 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[24].ram_18_22_28_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y160 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[25].ram_18_22_28_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y164 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[26].ram_18_22_28_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y168 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[27].ram_18_22_28_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y172 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[28].ram_18_22_28_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y176 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[29].ram_18_29_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
## ===========================================
set_property LOC RAMB36_X2Y120 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[30].ram_18_30_36_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y124 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[31].ram_18_30_36_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y128 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[32].ram_18_30_36_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y132 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[33].ram_18_30_36_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y136 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[34].ram_18_30_36_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y140 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[35].ram_18_30_36_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y144 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[36].ram_18_30_36_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y148 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[37].ram_18_37_43_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y152 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[38].ram_18_37_43_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y156 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[39].ram_18_37_43_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y160 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[40].ram_18_37_43_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y164 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[41].ram_18_37_43_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y168 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[42].ram_18_37_43_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y172 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[43].ram_18_37_43_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y176 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[44].ram_18_44_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
## ===========================================
set_property LOC RAMB36_X3Y120 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[45].ram_18_45_51_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y124 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[46].ram_18_45_51_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y128 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[47].ram_18_45_51_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y132 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[48].ram_18_45_51_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y136 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[49].ram_18_45_51_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y140 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[50].ram_18_45_51_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y144 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[51].ram_18_45_51_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y148 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[52].ram_18_52_58_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y152 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[53].ram_18_52_58_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y156 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[54].ram_18_52_58_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y160 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[55].ram_18_52_58_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y164 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[56].ram_18_52_58_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y168 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[57].ram_18_52_58_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y172 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[58].ram_18_52_58_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y176 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[59].ram_18_59_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
## ===========================================
set_property LOC RAMB36_X4Y120 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[60].ram_18_60_66_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X4Y124 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[61].ram_18_60_66_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X4Y128 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[62].ram_18_60_66_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X4Y132 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[63].ram_18_60_66_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X4Y136 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[64].ram_18_60_66_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X4Y140 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[65].ram_18_60_66_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X4Y144 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[66].ram_18_60_66_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X4Y148 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[67].ram_18_67_73_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X4Y152 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[68].ram_18_67_73_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X4Y156 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[69].ram_18_67_73_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X4Y160 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[70].ram_18_67_73_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X4Y164 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[71].ram_18_67_73_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X4Y168 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[72].ram_18_67_73_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X4Y172 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[73].ram_18_67_73_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X4Y176 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[74].ram_18_74_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
## ===========================================
set_property LOC RAMB36_X5Y120 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[75].ram_18_75_81_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y124 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[76].ram_18_75_81_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y128 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[77].ram_18_75_81_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y132 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[78].ram_18_75_81_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y136 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[79].ram_18_75_81_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y140 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[80].ram_18_75_81_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y144 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[81].ram_18_75_81_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y148 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[82].ram_18_82_88_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y152 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[83].ram_18_82_88_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y156 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[84].ram_18_82_88_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y160 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[85].ram_18_82_88_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y164 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[86].ram_18_82_88_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y168 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[87].ram_18_82_88_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y172 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[88].ram_18_82_88_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y176 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[89].ram_18_89_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
## ===========================================
set_property LOC RAMB36_X6Y120 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[90].ram_18_90_96_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y124 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[91].ram_18_90_96_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y128 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[92].ram_18_90_96_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y132 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[93].ram_18_90_96_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y136 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[94].ram_18_90_96_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y140 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[95].ram_18_90_96_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y144 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[96].ram_18_90_96_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y148 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[97].ram_18_97_103_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y152 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[98].ram_18_97_103_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y156 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[99].ram_18_97_103_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y160 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[100].ram_18_97_103_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y164 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[101].ram_18_97_103_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y168 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[102].ram_18_97_103_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y172 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[103].ram_18_97_103_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y176 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[104].ram_18_104_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
## ===========================================
set_property LOC RAMB36_X7Y120 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[105].ram_18_105_111_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y124 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[106].ram_18_105_111_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y128 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[107].ram_18_105_111_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y132 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[108].ram_18_105_111_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y136 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[109].ram_18_105_111_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y140 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[110].ram_18_105_111_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y144 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[111].ram_18_105_111_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y148 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[112].ram_18_112_118_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y152 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[113].ram_18_112_118_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y156 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[114].ram_18_112_118_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y160 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[115].ram_18_112_118_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y164 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[116].ram_18_112_118_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y168 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[117].ram_18_112_118_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y172 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[118].ram_18_112_118_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y176 [get_cells $SLR2_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[119].ram_18_119_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
